Power management parts typically have at least two power domains: analog and power. The analog domain is generally free of noise while the power domain, by definition, will have a lot of noise from the switching transistors (inductive transients).
Proper Electrostatic Discharge (ESD) protection for integrated circuits (ICs), such as power management parts, requires a defined current path between each pin combination. This requirement poses problems from a circuit design perspective when it is desired to keep the noisy switching power domain separate from the quiet analog domain. The supplies may be at different potentials (i.e. 5 V and 12 V) making coupling the power domains difficult.
The simplest solution, since both grounds are at zero volts, is to put anti-parallel diodes between the two grounds thereby tying the two domains together. This separates the grounds by a diode drop and the diode capacitance. Since transients, switching noise, on the power domain may exceed 3 volts, a single diode drop of 0.7 V will not provide adequate isolation so additional diodes may be needed. However, with each added diode the series resistance increases from an ESD perspective. If the resistance is kept the same, the diodes would have to be Nx in size for N diodes in series. To achieve 3 volt isolation with the anti-parallel diode solution, it would require approximately 5 to 6 diodes in series. This would result in an extremely large ESD protection structure, which would make it undesirable for most applications.
Another possible protection scheme is to provide cross coupled clamps between the two power domains. This has been used and does provide good ground to ground isolation but in effect doubles the number of clamps that are required to achieve optimum protection. For a circuit with many power domains this could become prohibitive since each quiet power domain would have to be coupled to each noisy domain. Another drawback with this approach is that the noise on the noisy domain could falsely trigger the ESD clamps required in the cross coupling resulting in an electrical overstress (EOS) event damaging the circuit in question.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an effective and efficient ESD clamp that uses a relatively small footprint.